Semiconductor devices having standard cell library logic (“standard cells”) often utilize a metal power rail to bring power and ground to the transistors forming the standard cells. In a common layout technique, standard cells are positioned above and below the power rail to maximize use of the power rail. A contact spine is typically disposed underneath and parallel to the power rail. A plurality of vias connects the metal rail to the contact spine. This contact spine is then electrically connected to contacts, which in turn, connect to the transistors.
Typically, the pitch of the vias (i.e., the spacing between the vias) is larger than the pitch of the gates of the transistors. Most often, the via pitch is double that of the gate pitch. However, the use of such a via pitch increases the resistance between the power rail and the transistors, thus reducing the electric performance of the transistors.
Accordingly, it is desirable to utilize a technique for more effective spacing between vias. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.